Graphic Designers

**Company Description**

Pay Rates Starting between: $14.70 - $19.00 / hour

Are you passionate about team building, customer service, and meeting new people? Pilot Company offers a dynamic environment where no two days are the same. Team members have the opportunity to build an inclusive atmosphere with their co-workers and make a better day for every type of guest – whether it’s the professional driver stopping for a clean shower, the commuter grabbing their morning coffee, or the vacationer needing their go-to snack along their journey. We embrace and celebrate our diverse guests and team members, who fuel creativity, innovation, and positivity. We strive to make every stop on your career journey — and our guests’ journey — a great one!

Also, there are a number of opportunities to work in other roles within our travel centers and restaurants so while we may be hiring for a specific role, we always look to train and offer experience for other roles we have.

We hope your next career stop is with us! Join our team and start your journey with Pilot Flying J.

**BENEFITS**

+ Weekly Pay

+ 15 cent fuel discount

+ Free daily meals

+ $10 low-cost health plans (for full-time team members)

+ Paid time off

+ Family leave

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, protected veteran status or any other characteristic protected under applicable federal, state, or local law.

Military encouraged to apply.

**Job Description**

+ Provide guests fast, friendly, and clean service

+ Maintain inventory

+ Manage and prep food safely

+ Ensure top-notch quality in all our food products

+ Operate cash registers

+ Maintain the overall appearance and cleanliness of the restaurant

+ Provide excellent guest service

**Qualifications**

**Required Qualifications**

+ Incredible guest service skills and ability to maintain a guest focused culture

+ Ability to complete accurate sales transactions

+ Ability to cleanly and safely manage and prep food

+ Ability to maintain Subway processes and policies

+ Ability to use computers, telephones, and other equipment as needed

+ Ability to work as part of a team

**Preferred Qualifications**

+ Experience in a similar position

+ Ability to work a flexible schedule of nights, days, weekends, and holidays

**Additional Information**

+ Wellness Program

+ Reward and Recognition Program

+ Professional development

+ 401(k) retirement savings plan

+ Paid parental leave

+ Adoption Assistance

+ Flexible Schedule

+ Full and Part Time positions available

**Senior MTS Analog Design**

**onsemi** is seeking a Senior MTS Analog design Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Scottsdale Arizona, USA. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and e-fuses for consumer, industrial and automotive applications. In this role, you will focus on the following

**onsemi** (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.

**More details about our company benefits can be found here:**
https://www.onsemi.com/careers/career-benefits

We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.

**onsemi** is an Equal Opportunity and Affirmative Action employer. The Company maintains policies and practices that are designed to prevent discrimination or harassment against any qualified applicant or employee to the extent prohibited by federal, state and local laws and regulations. By way of example, discrimination on the basis of race (actual or perceived), ethnicity, color, religion, ancestry, national origin, citizenship, sex, age, marital status, sexual orientation, physical or mental disability, medical condition, genetic information, military or veteran status, gender identity, gender expression, or any other characteristic protected by applicable law is prohibited.

If you are an individual with a disability and require a reasonable accommodation to complete any part of the application process, or are limited in the ability or unable to access or use this online application process and need an alternative method for applying, you may contact Talent.acquisition@onsemi.com for assistance.

**Summary:**

Meta Metaverse Creative’s mission is to build tools that help people feel connected, anytime, anywhere. Lifelike, interactive characters are an important part of this mission. As an Animator on the team, you’ll be working with a talented group of industry professionals leading the way in this emergent and creative space. If you’re excited about forging into new territory and pushing the boundaries of real-time character animation across a variety of media and genres, this may be the place for you.

**Required Skills:**

Animator Responsibilities:

1. Create and push the craft of real-time and pre-rendered character animation through hand-authored, tracked, and procedural methodologies.

2. Create emotion and expressivity through facial animations.

3. Create believable and visually appealing full-body character animations and poses.

4. Work with the Art Director, Animation Leadership, Product Team, Design, UXR and the immediate creative team to collaborate, pre-visualize, and create great animation for VR/AR and 2D media.

5. Communicate with the Engineers, Tech Artists and Character Artists to develop and improve animation systems (facial, cinematic, move-tree, procedural) that will raise the bar within the required technical constraints.

6. Work with multiple vendors, collaborating and giving feedback on technical and artistic solutions.

7. Proactively identify areas in the production pipelines and execution to improve and actively participate in cross-functional settings to create solutions.

8. Collaborate with the Animation team to create memorable, emotive characters.

9. Find solutions to technical challenges and improve animation methodology within pipelines.

**Minimum Qualifications:**

Minimum Qualifications:

10. Proven capacity to multitask and handle both large-scope projects and execute on granular work simultaneously.

11. Proven teamwork and communication skills, experience to receive and offer feedback.

12. Experience creating industry leading, key-frame animation for vfx, film, games or real-time applications.

13. Experience working within distributed/remote team environment and/or animation vendors.

**Preferred Qualifications:**

Preferred Qualifications:

14. Proficiency in Motion Capture Animation in MotionBuilder.

15. Real time animation experience.

16. Experience working in VR/AR environments.

**Public Compensation:**

$149,000/year to $205,000/year + bonus + equity + benefits

**Industry:** Internet

**Equal Opportunity:**

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.

**Job Details:**

**Job Description:**

Seize the opportunity to work with the team responsible for RTL logic design and verification of chipsets for PCs millions of people around the world will use. The Chipsets Logic Team, CLIPS is responsible for developing soft IPs, subsystems and gaskets for Client Computing Group projects. This job requisition is to seek an experienced, disciplined and collaborative IP design verification engineer in Folsom, California.

As a member of the Chipsets Logic Design Verification team, you will:

+ Work closely with IP architects to define and develop verification testbench and building RTL models for verification.

+ Verify the functionality of new architectural features using both functional and formal verification methods of next generation designs by developing test plan, tests content or test tools.

**Qualifications:**

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

+ Bachelor’s Degree in Electrical or Computer Science Engineering or related field with 12+ years of technical experience or Master’s Degree with 10+ years of technical experience or PhD 8+ years of technical experience.

+ 6+ years of experience in Formal Verification tools, methodologies, and technologies.

+ 4+ years of experience in driving cross organizational work group aimed at new IP adoption of Formal Verification

+ Must have completed multiple iterations of verification life cycles (verification architecture, test plan, execution, debug, coverage closure).

Preferred Qualifications:

+ 6+ years of experience in Functional Verification of IP by defining verification strategy, test plans, test benches and environment.

+ Experience in OVM/UVM, AMBA protocols, PCI express or any industry standard BUS protocol.

+ Successful track record of hardware development experience collaborating with SoC architects, micro architects, full chip architects, RTL developers and post silicon

+ Demonstrated technical leadership by solving highly complex technical problems with excellent communication skills.

+ Demonstrated strong ethical standards while performing in a highly ambiguous and dynamic business environment.

+ Skills: UVM, AMBA protocols, System Verilog, IP sub-system DV.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

**Job Type:**

Experienced Hire

**Shift:**

Shift 1 (United States of America)

**Primary Location:**

US, California, Folsom

**Additional Locations:**

US, Arizona, Phoenix, US, California, Santa Clara

**Business group:**

The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

**Posting Statement:**

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

**Position of Trust**

N/A

**Benefits:**

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
https://jobs.intel.com/en/benefits

Annual Salary Range for jobs which could be performed in the US:

$161,230.00-$227,620.00

**S** **al** **ary** **range** **dependent on a number of factors including location and experience.**

**Work Model for this Role**

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

**Job Details:**

**Job Description:**

Technology Development (TD) is the heart and soul of Moore's Law at Intel, enabling Intel to create world-changing technology that enriches the lives of every person on earth. TD drives breakthrough research and develops next generation process/packaging technologies, while also running high volume manufacturing operations in its state-of-the-art facilities in Oregon and Arizona. The Design Technology Platform (DTP) team in TD works closely with the technology team to maximize the value proposition of the technology for our customers thru Design Technology Co-Optimization (DTCO), delivers the Process Design Kits (PDKs), foundational IPs (FIPs), and the Intel Foundry reference flows. These same deliverables carry out technology lead vehicle execution for Si validation. Enablement and optimization of reference flows and design flows on Intel technology play a crucial role in accomplishing DTP's charter.

Design flow development engineer will work in a team responsible for architecting, executing, and delivery of the EDA design flow for all DTCO activities, technology lead vehicle design, IP design, and product design in TD. The design flow will be built on top of a reference flow enabled on Intel technology and released from external EDA vendors. The design flow covers all aspects of front-end and back-end design from RTL to GDS, digital and analog, design creation, verification, and signoff. The candidate must be result-oriented and capable of disciplined flow execution to meet delivery milestones in a fast-paced environment on advanced technology nodes. Prior experience in EDA tool/flow and design environment development is highly desirable. Familiarity with automated SoC design methodology and/or analog/mixed-signal design methodology is a big plus.

**Qualifications:**

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

**Minimum Qualification:**

+ Candidate must have a BS, MS, or PhD degree in electrical engineering, computer engineering or similar field.

+ BS + 10 years or M.S./Ph.D. + 7 years of experience in the development of EDA tools, flows and/or design env for digital or analog designs with demonstrated strong programing skills.

+ Working knowledge in digital and/or analog Si design and methodology.

**Preferred Qualifications:**

+ Working knowledge with major (EDA) software platforms (Synopsys, Cadence, Siemens).

+ Working knowledge of all aspects of digital SoC in a product setting - floorplanning, RTL design, logic synthesis, place and route, clock tree construction, extraction and timing signoff, signal integrity analysis, layout and reliability verification, and full chip integration.

+ Working knowledge of key aspects of Analog tools - schematic entry, custom layout editing, extraction, simulation, reliability, and signoff.

+ Demonstrated experience in establishing and qualifying digital or analog design flow from an EDA reference flow and addressing product specific design/methodology requirements and design database management.

+ Demonstrated ability to understand and interpret industry EDA trend in response to advanced node requirements, drive design flow initiatives to align.

+ Excellent written and verbal communication skills.

**Job Type:**

Experienced Hire

**Shift:**

Shift 1 (United States of America)

**Primary Location:**

US, Oregon, Hillsboro

**Additional Locations:**

US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, Austin

**Business group:**

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

**Posting Statement:**

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

**Position of Trust**

N/A

**Benefits:**

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
https://jobs.intel.com/en/benefits

Annual Salary Range for jobs which could be performed in the US:

$161,230.00-$227,620.00

**S** **al** **ary** **range** **dependent on a number of factors including location and experience.**

**Work Model for this Role**

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

**Job Details:**

**Job Description:**

Come join us as a Physical Design Engineer and together let's grow and develop the next leading technology.

**Key Responsibilities:**

+ Lead physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.

+ Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.

+ Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.

+ Analyzes results and makes recommendations to fix violations for current and future product architecture.

+ Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.

+ Optimizes design to improve product level parameters such as power, frequency, and area.

+ Participates in the development and improvement of physical design methodologies and flow automation.

The candidate should exhibit the following:

+ Excellent problem solving and communication skills

**Qualifications:**

**Minimum Qualifications:**

The candidate must have a Bachelor's Degree in Electrical/Computer Engineering, Computer Science, or related major with 10+ years' experience - **OR** - a Master's Degree in Electrical/Computer Engineering, Computer Science, or related major with 8+ years' experience with:

+ Block/Top Floor planning , Synthesis and Place and Route, STA (preferably in complex Mixed-Signal blocks involving multiple analog blocks)

+ Technical lead for RTL2GDS at block/top level OR STA lead of block/top level

+ Industry standard tools (eg. Fusion Compiler, Primetime, Conformal etc.)

+ Scripting languages (eg. TCL, Perl, Python etc.)

**Preferred Qualifications:**

+ 8+ years of experience in Physical Design

+ Synthesis and PNR flows on Multi-Voltage/Low Power designs with greater than 1M instances

+ Good understanding of low power rule verification, Clock distribution schemes, Timing constraint analysis and feedback to Front-End teams, Static Timing analysis, Timing ECO Generation at block/top level.

+ Handson experience in scripting using EDA tool API interface for Cadence or Synopsys

+ Prior experience in being a technical lead for junior engineers driving Synthesis/Place and Route or STA or Physical Verification or Electrical Verification tasks

+ Excellent Scripting skills in Perl or Python

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

**Job Type:**

Experienced Hire

**Shift:**

Shift 1 (United States of America)

**Primary Location:**

US, California, Folsom

**Additional Locations:**

US, Arizona, Phoenix, US, California, Santa Clara

**Business group:**

The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

**Posting Statement:**

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

**Position of Trust**

N/A

**Benefits:**

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
https://jobs.intel.com/en/benefits

Annual Salary Range for jobs which could be performed in the US:

$186,070.00-$262,680.00

**S** **al** **ary** **range** **dependent on a number of factors including location and experience.**

**Work Model for this Role**

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

**Job Details:**

**Job Description:**

Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Who We Are

Exciting opportunity to be a part of NXNE DFT team

The Design-for-Test (DFT) Implementation Engineer is a challenging and cutting-edge position working as part of a team to implement Design-for-Test capabilities on state-of-the-art silicon designs. You will be working with both external tier-1 customers and internal product design teams during their ASIC design cycle as they develop System-on-a-Chip (SoC) solutions utilizing CMOS cell-based ASIC technologies, along with integrated high-performance SerDes functions, embedded microprocessors, and high speed memory interface IP.

Who You Are

Your job responsibilities will include but not limited too:

+ You will be responsible for development of the SoC Test Implementation plan describing the strategies to address the DFT requirements for the design, planning of the hierarchical test architecture, insertion of DFT structures, generation, simulation, and validation of test patterns for both DFT logic verification and for HVM ATE testing of the design, supporting the Static Timing Analysis (STA) team for the timing closure for the DFT modes of the design, and for supporting the Test Engineering team during silicon bring-up and New Product Introduction (NPI).

+ You will also work closely with internal Test Methodology team and IP development teams.

+ Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN)

+ Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST)

+ Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE)

+ Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. Optimizes logic to qualify the design to meet power, performance, area, timing, testcoverage, DPM, and testtime/vectormemory reduction goals as well as design integrity for physical implementation

+ Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications

+ Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure highquality integration of the IP block

+ Collaborates with postsilicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation.

+ Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.

**The ideal candidate will exhibit the following :**

+ Good problem-solving skills and a self-starter.

+ Independently drive solutions to complex problems

+ Ability to comprehend content of technical specifications for SoC Design-For-Test (DFT) principles including SCAN for logic testing, BIST and repair for memory test, JTAG Boundary SCAN

+ Effective communication and collaboration skills.

+ Ability to work effectively in a cross-site team environment.

**Qualifications:**

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

+ Bachelor's degree in Electrical engineering, Computer science , Electronics and Communications Engineering with 6+ years of industry experience

+ OR Master's degree in Electrical Engineering, Computer science, Electronics and Communications Engineering with 4+ years of industry experience

Your experience should be in the following:

+ SoC Design-For-Test (DFT) principles including SCAN for logic testing, BIST and repair for memory test, JTAG Boundary SCAN

+ Test insertion, test pattern generation, simulation, and verification

+ Industry-standard DFT tools such as Mentor Graphics Tessent, Synopsys DFT Compiler, DFTMax, TetraMax

+ DFT architecture development and planning for an SoC

Preferred Qualifications:

+ Knowledge of manufacturing tester capabilities, Automatic Test Equipment (ATE), and test program experience

+ Knowledge of DFT integration of IP (e.g. DDR, SerDes, PLL's) into an SoC

+ Static Timing Analysis, Synopsys PrimeTime, constraints and timing path debug

+ Scripting Languages, e.g., PERL, TCL/Tk, Python

**Job Type:**

Experienced Hire

**Shift:**

Shift 1 (United States of America)

**Primary Location:**

US, Texas, Austin

**Additional Locations:**

US, Arizona, Phoenix, US, California, Santa Clara

**Business group:**

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

**Posting Statement:**

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

**Position of Trust**

N/A

**Benefits:**

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
https://jobs.intel.com/en/benefits

Annual Salary Range for jobs which could be performed in the US:

$161,230.00-$227,620.00

**S** **al** **ary** **range** **dependent on a number of factors including location and experience.**

**Work Model for this Role**

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

**Job Details:**

**Job Description:**

Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Want to learn more? Visit our YouTube Channel or the links below.

Life at Intel (https://jobs.intel.com/en/life-at-intel)

Diversity at Intel

This role is within Intel’s Client Computing Group. CCG is a computing paradigm where services and data reside in scalable data centers, and those services and data can be accessed by any connected device over the Internet. Responsible for designing and optimizing processors, chipsets and other hardware for consumer devices while also working on the software ecosystem, including drivers and utilities that enhance user experience.

The Edge Platform Product Management team within CCG's Edge Computing Group is looking for a passionate, self-driven technical product manager to help define, manage and deliver base platform technologies and ingredients to support Intel's Edge systems and solutions. The candidate will apply strategic thinking and world class product management practices to establish the POR across the product swim-lanes with a customer first, full system mindset.

The position requires a combination of business acumen, organization savvy, networking capabilities and system expertise.

Activities include among others:

+ Competitive analysis and market research to develop strategic plans and marketing requirements with an outside-in perspective from customers and developers.

+ Partner with vertical business units, architecture and engineering teams to manage the technology POR throughout the Product Lifecycle from strategic planning to launch.

+ Manage the horizontal platform capabilities portfolio including business priorities and budget, serving as one-voice outbound to customers and internally to engineering teams.

+ Support Go-to-Market motions jointly with ecosystem and customer enabling organizations.

The Technology Product Manager should possess the following attributes:

+ Excellent communication skills, stakeholder management and ability to convey complex technical issues to senior leaders.

+ Strong planning and project management skills.

**Qualifications:**

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

**What we need to see (Minimum Qualifications):**

· Bachelor's degree in computer science, electrical/computer engineering or equivalent with 8+ years relevant experience or Master's degree in computer science, electrical/computer engineering or equivalent with 6+ years relevant experience.

· 5+ years of experience in any of the following areas: delivering products, platform software (BIOS/FW, drivers, OS, virtualization) or platform technologies (Security, Manageability, Graphics/Media/Display, Camera Sensors, Real-Time or AI) to client, Edge or data center markets.

· 5+ years of experience working with customers, business and technical teams to translate business requirements into technical requirements and deliverables.

**Preferred Qualifications:**

· Bachelor's degree in computer science, electrical/computer engineering or equivalent with 10+ years or Master's degree in computer science, electrical/computer engineering or equivalent with 8+ years in computer science, electrical/computer engineering or equivalent.

· Hands-on experience delivering solutions for Edge segments (Industrial, Retail, Health, Education, etc.)

· Well versed with x86 architecture and base platform software concepts.

· Experience working with platform ecosystem (OEM/ODM, IBV, OSV, ISV, SI) to deliver commercial ready platforms.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

**Benefits at Intel**

Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers (https://jobs.intel.com/en/benefits) for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion.

**Job Type:**

Experienced Hire

**Shift:**

Shift 1 (United States of America)

**Primary Location:**

US, Arizona, Phoenix

**Additional Locations:**

US, California, Santa Clara, US, Oregon, Hillsboro

**Business group:**

The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

**Posting Statement:**

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

**Position of Trust**

N/A

**Benefits:**

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
https://jobs.intel.com/en/benefits

Annual Salary Range for jobs which could be performed in the US:

$183,040.00-$258,410.00

**S** **al** **ary** **range** **dependent on a number of factors including location and experience.**

**Work Model for this Role**

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

**Job Details:**

**Job Description:**

Intel Federal LLC is a wholly owned subsidiary of Intel Corporation responsible for managing Intel's business with the US Federal Government. We collaborate with sales and marketing, government affairs, and Intel business units to develop and execute programs for US Government (USG) agencies. Intel Federal works with and across the defense industrial base and systems integrator ecosystem to deliver mission solutions to USG customers.

We are seeking a skilled Technology Product Manager to translate long-term business objectives into actionable technology product strategies and implementation roadmaps. You will drive all portfolio decisions, including product goals, roadmaps, forecasts, and backlog prioritization, with customer satisfaction as a key business lever. You will represent the technical group as a strategic partner of an Intel business unit for full-stack business process solutions and own the delivery of a portfolio of technical products and capabilities.

**Responsibilities:**

+ Exhibit expertise in federal government and people management skills.

+ Manage and drive project management resource to ensure the team is prepared to lead scope, analyze, and plan activities for projects.

+ Excellent problem solving, analytical, written, and communications skills.

+ Summarize complex and diverse technical subjects succinctly to non-technical audiences.

+ Coordinate with all stakeholders to facilitate clear and simple communication regarding project/program choices and issues.

+ Lead review with executives and department leads for large-scale programs, provide transparency into the health, risk, and financials of individual projects.

+ Prioritize deliverables to meet strategic needs.

+ Handle escalations, resolve issues, and take corrective actions as required.

+ Learn fast and comfortable in environments while rapidly leading teams through ambiguous objectives in a structured way.

+ Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results.

+ Drive results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment.

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**Qualifications:**

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Job posting details (such as work model, location, or time type) are subject to change.

+ US Citizenship required.

+ Ability to obtain a US government security clearance.

+ Bachelor’s degree with 9+ years of experience, OR a Master's degree with 6+ years of experience, OR a PhD with 4+ years of experience in Program Management, Computer Science, or a related field with emphasis in technology.

+ 6+ years of experience with Technical Product Management or Software Development/Management practices.

+ 5+ years of leadership experience managing engagements across various teams and stakeholders.

+ Experience leading programs for Enterprise Application development or SAP ecosystem.

**Preferred qualifications**

+ Active U.S. Government TS Security Clearance.

+ Experience working on programs with federal information handling and security requirements.

+ Experience in semiconductor industry, technology and industry partners.

+ Experience implementing and maintaining FedRAMP compliant Enterprise Resource Planning, Customer Relationship Management, and Contract Lifecycle Management solutions.

**Job Type:**

Experienced Hire

**Shift:**

Shift 1 (United States of America)

**Primary Location:**

US, Oregon, Hillsboro

**Additional Locations:**

US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Texas, Austin, US, Virginia, Fairfax

**Business group:**

Intel's Information Technology Group (IT) designs, deploys and supports the information technology architecture and hardware/software applications for Intel. This includes the LAN, WAN, telephony, data centers, client PCs, backup and restore, and enterprise applications. IT is also responsible for e-Commerce development, data hosting and delivery of Web content and services.

**Posting Statement:**

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

**Position of Trust**

N/A

**Benefits:**

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
https://jobs.intel.com/en/benefits

Annual Salary Range for jobs which could be performed in the US:

$183,040.00-$258,410.00

**S** **al** **ary** **range** **dependent on a number of factors including location and experience.**

**Work Model for this Role**

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

**Job Details:**

**Job Description:**

In this role, we are looking for an experienced SOC Analog Engineer to lead Analog Integration for chiplet designs for custom and domain specific products. The chiplets will be leveraged to enable modular design and support multiple products. As part of this team, the candidate will work with leading edge technologies and solutions across multiple domains including SoC multi-die implementations (2.5 and 3D), power delivery, leading edge memory technologies, innovate thermal solutions, and external vendors. The team will also look at options to enhance product power/performance/area/cost thru improved tools and methodologies.

Responsibilities will include but are not limited to:

+ Drive all aspects of analog integration domain, including analog route implementation/extraction/verification, AIP floor planning, PKG interactions w/ analog IOs, power framework simulations, ESD planning/verification, MIM, and GPIO planning

+ Collaborate across multiple teams/stakeholders to create optimal solutions across Platform/PKG/SoC

+ Create, run, and analyze simulations for design and verification of analog circuitry such as amplifiers, reference systems, ESD, and high-speed Rx/Tx circuitry

+ Scope process technologies and enable integration of Analog IP and silicon supplied by external vendors

+ Support post-silicon activities in debug and failure analysis for analog and power delivery

The ideal candidate should exhibit the following behavioral traits/skills:

+ Have expertise with domain specific signoff tools including: HV Openrail, Redhawk, LV/antenna checks.

+ Have experience with IP design, packaging and delivery methodologies and flows as well as generation of IP integration documents and datasheets

**Qualifications:**

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

**Minimum Qualifications:**

+ Bachelor's or Master's degree in Computer Science, Computer Engineering or Electrical Engineering.

+ 6+ years of Analog design experience including Analog integration and AIP design

+ 6+ years experience with SoC analog requirements, including analog distributions, and ESD.

**Preferred Qualifications:**

+ Experience with Design tools and methods.

+ Full chip integration, die-to-die and package integration experience.

+ 2.5/3D design experience and implications on analog design.

+ Experience with power delivery design and flows

**Job Type:**

Experienced Hire

**Shift:**

Shift 1 (United States of America)

**Primary Location:**

US, Massachusetts, Beaver Brook

**Additional Locations:**

US, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro

**Business group:**

The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

**Posting Statement:**

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

**Position of Trust**

N/A

**Benefits:**

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
https://jobs.intel.com/en/benefits

Annual Salary Range for jobs which could be performed in the US:

$186,070.00-$262,680.00

**S** **al** **ary** **range** **dependent on a number of factors including location and experience.**

**Work Model for this Role**

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.