**Job Details:**

**Job Description:**

Come join us as a Physical Design Engineer and together let's grow and develop the next leading technology.

**Key Responsibilities:**

+ Lead physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.

+ Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.

+ Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.

+ Analyzes results and makes recommendations to fix violations for current and future product architecture.

+ Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.

+ Optimizes design to improve product level parameters such as power, frequency, and area.

+ Participates in the development and improvement of physical design methodologies and flow automation.

The candidate should exhibit the following:

+ Excellent problem solving and communication skills

**Qualifications:**

**Minimum Qualifications:**

The candidate must have a Bachelor's Degree in Electrical/Computer Engineering, Computer Science, or related major with 10+ years' experience - **OR** - a Master's Degree in Electrical/Computer Engineering, Computer Science, or related major with 8+ years' experience with:

+ Block/Top Floor planning , Synthesis and Place and Route, STA (preferably in complex Mixed-Signal blocks involving multiple analog blocks)

+ Technical lead for RTL2GDS at block/top level OR STA lead of block/top level

+ Industry standard tools (eg. Fusion Compiler, Primetime, Conformal etc.)

+ Scripting languages (eg. TCL, Perl, Python etc.)

**Preferred Qualifications:**

+ 8+ years of experience in Physical Design

+ Synthesis and PNR flows on Multi-Voltage/Low Power designs with greater than 1M instances

+ Good understanding of low power rule verification, Clock distribution schemes, Timing constraint analysis and feedback to Front-End teams, Static Timing analysis, Timing ECO Generation at block/top level.

+ Handson experience in scripting using EDA tool API interface for Cadence or Synopsys

+ Prior experience in being a technical lead for junior engineers driving Synthesis/Place and Route or STA or Physical Verification or Electrical Verification tasks

+ Excellent Scripting skills in Perl or Python

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

**Job Type:**

Experienced Hire

**Shift:**

Shift 1 (United States of America)

**Primary Location:**

US, California, Folsom

**Additional Locations:**

US, Arizona, Phoenix, US, California, Santa Clara

**Business group:**

The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

**Posting Statement:**

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

**Position of Trust**

N/A

**Benefits:**

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
https://jobs.intel.com/en/benefits

Annual Salary Range for jobs which could be performed in the US:

$186,070.00-$262,680.00

**S** **al** **ary** **range** **dependent on a number of factors including location and experience.**

**Work Model for this Role**

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.